1. Field of the Invention
Embodiments of the present invention generally relate to analog and digital signal distribution/synchronization methods and systems and in particular to the distribution of a modulated signal in a coherent system to achieve carrier phase/frequency synchronization at the distribution points.
2. Description of the Related Art
Many analog and digital systems and subsystems used in communications, computing, data processing, military, and other applications (collectively hereinafter referred to as “coherent systems”) are designed to operate synchronously. Typical coherent systems comprise subsystems capable of generating and transmitting signals such as electronic, electrical, mechanical, optical, or sonar subsystems. An example of an electronic coherent system is the massive set of logic gates present in modern digital systems or subsystems. These gates switch according to an absolute clock beat, which is provided by properly generated or distributed clock signals. Typically, the local clock signals are distributed from a master clock source. In order to reduce system level EMI (electromagnetic interference), this clock signal is sometimes modulated with low frequency signals or noise. For example, this technique is often used in VLSI systems. In such a case, the distributed “clock” signal is a phase-modulated carrier, which is non-periodic, albeit with approximately periodic shape over short time intervals. The distribution network must guarantee accurate carrier synchronization such that all logic is clocked properly from clock beat to clock beat, even though in the long run the phase of the clock signal wanders around an average absolute value.
In addition to digital applications, there are many analog, RF, and mixed-signal systems, which require time synchronization of modulated signals. For example, active arrays, such as phased-array radars or electronic steering antennas rely on precise carrier phasing of RF signals. The distribution of these modulated signals is similar in concept to the clock distribution in digital systems.
A typical signal distribution network with phased aligned outputs is built hierarchically using a tree topology, starting with a master generator connected to a tree trunk to which branches are attached, followed by other branches, etc. until the final signal delivery points are reached on top of the tree. If the distribution network is electrically small for the carrier frequency used, i.e., if the signal propagation times from the generator to any of the final delivery points are small compared to the carrier period, the tree network as described without any additional constraints is adequate. However, in most modern applications, the carrier frequencies are so high (e.g., on the order of GHz) that even miniaturized systems, such as fully integrated circuits, are not electrically small. In such cases, the design of the distribution network providing accurate synchronization may become extremely challenging.
A known approach to signal distribution in electrically-large systems is based on the “equal time-of-flight” principle. The distribution network is designed such that the time necessary for a signal to propagate from the master generator to all delivery points at the top of the tree is a constant. The RF corporate feed network or the VLSI H-tree clocking network are typical examples implementing this principle. This approach is the de facto “work horse” of signal distribution/synchronization but suffers from well-documented practical limitations: stringent geometrical constraints, power hungry, susceptibility to noise, and susceptibility to timing errors known as skew. Often, expensive additional techniques are employed to contain these shortcomings. In the case of active distribution trees, such as those used in VLSI clocking, operation at frequencies above a few GHz is rather difficult to attain. Recently, serial clock distribution over wave guides has been proposed, motivated by improved theoretical performance in power dissipation, noise and cost. For example, see Wayne D Grover “Method and Apparatus for Clock Distribution and for Distributed Clock Synchronization,” U.S. Pat. No. 5,361,277, Nov. 1, 1994; Michael Farmwald and Mark Horowitz, “Apparatus for Synchronously Generating Clock Signals in a Data Processing System” U.S. Pat. No. 5,243,703, Sep. 7, 1993; Charles D. Miller “Signals Distribution System” U.S. Pat. No. 5,712,882, Jan. 27, 1998; NRAO, A Proposal for a Very Large Array Radio Telescope, Vol. II, National Radio Astronomy Observatory, Green Bank, West Va., Ch. 14, 1967; Richard R Goulette “Technique for Distributing Common Phase Clock Signals” U.S. Pat. No. 6,531,358 B1, May 13, 2003; and V. Prodanov and M. Banu “GHz Serial Passive Clock Distribution in VLSI Using Bidirectional Signaling,” Proceedings, 2006 IEEE Custom Integrated Circuits Conference. The inherent skew accumulation due to serial transmission is mitigated by time averaging two signals propagating in opposite directions. The main fundamental shortcomings of this technique are a) the large total length of the waveguides, possibly resulting in signal loss and dispersion, and b) the limited practical precision of the known time averaging circuits. In addition, these methods were intended for distribution of periodic, not modulated, signals.
A first class of previously proposed serial clock distribution schemes: See Wayne D. Grover “Method and Apparatus for Clock Distribution and for Distributed Clock Synchronization” U.S. Pat. No. 5,361,277, Nov. 1, 1994; Michael Farmwald and Mark Horowitz, “Apparatus for Synchronously Generating Clock Signals in a Data Processing System” U.S. Pat. No. 5,243,703, Sep. 7, 1993; and Charles D. Miller “Signals Distribution System” U.S. Pat. No. 5,712,882, Jan. 27, 1998, uses electrical pulse signaling over transmission lines. For these techniques, any pulse dispersion introduces timing errors, which increase as the pulses travel farther and farther away from the generators. The theoretical possibilities to avoid these errors at high frequencies are either to use extremely good, low-dispersion transmission lines, or to keep the total length of the transmission lines short. The first option increases the system cost and the second option reduces the number of useful applications. Applying this approach with high speed optical pulses transmitted over optical wave-guides should provide significantly lower dispersion but such systems would require additional error-prone functionality related to optical-to-electrical conversion.
A second class of proposed serial clock distribution schemes, see NRAO, A Proposal for a Very Large Array Radio Telescope, Vol. II, National Radio Astronomy Observatory, Green Bank, West Va., Ch. 14, 1967; Richard R Goulette “Technique for Distributing Common Phase Clock Signals” U.S. Pat. No. 6,531,358 B1, May 13, 2003; and V. Prodanov and M. Banu “GHz Serial Passive Clock Distribution in VLSI Using Bidirectional Signaling,” Proceedings, 2006 IEEE Custom Integrated Circuits Conference, use electrical sinusoidal excitations over transmissions lines and analog multipliers for time averaging. One advantage of single tone signaling is the elimination of dispersion as a negative factor in system performance. Moreover, the use of multipliers seems attractive due to the apparent simplicity of this scheme. However, this theoretical simplicity is deceptive.
On a closer analysis, it becomes clear that the precision of the overall scheme depends on the quality of the analog multipliers that can be realized in practice. Of particular relevance is the multiplier output harmonic purity. Typical high frequency multiplier circuits such as those used as RF mixers generate outputs rich in harmonics. Such circuits cannot be used for accurate time averaging because the output harmonics introduce significant timing errors. Therefore, special analog multiplier circuits with low harmonic output content are needed. This is not a trivial design task for low cost applications such as VLSI clocking, where using integrated RF filters to clean up each multiplier output would not be economical. The design of integrated multipliers with very low harmonic content is further complicated if the two multiplier inputs do not have the same magnitude. Therefore, in practice, the signal loss over the transmission lines must be maintained low. Just as before, this limits the technique either in terms of cost through the requirement of implementing expensive low-loss transmission lines, or in limited application possibilities due to short total transmission line length.